In a dynamic semiconductor memory circuit, each memory cell includes a storage capacitor which is charged to one of two voltage states which correspond to binary information. The charge on the storage capacitor has a short life time due to leakage within the cell. The charge must be periodically refreshed to maintain the data pattern stored in the memory. Reading the memory cell comprises connecting the storage capacitor to a digit line so that the charge stored on the capacitor is transferred to the digit line. The transfer of charge causes the voltage on the digit line to be changed by a few tenths of a volt, and this voltage change is detected by a sense amplifier which makes a comparison to the voltage on a complementary half of the digit line. The ability to correctly read the charge stored on the storage capacitor is dependent upon the voltage on the capacitor at the time that it is read. To insure the greatest accuracy in storing data, it is important to initially charge the storage capacitor to the highest possible voltage. In an MOSFET (metal oxide semiconductor field effect transistor) memory circuit it is most desirable to use a single +5 volt voltage supply. When using the one supply, it is therefore important that when storing the information represented by the high voltage state, the full 5.0 volts be applied to the memory cell.
Heretofore dynamic RAM (Random Access Memory) circuits have utilized digit lines which are charged by driving circuitry to substantially the supply voltage to place a high voltage level into a memory cell. But due to the resistance and capacitance of the digit line and corresponding input/output line, a substantial time is required to charge the digit line to approximately the supply voltage. There is an increasing demand for memory circuits which have faster operating cycles and the process described above for charging digit lines is inherently slow and as such cannot meet the demand for greater speed.
In view of the above problems, there exists a need for a method of operating a dynamic integrated circuit semiconductor memory in such a manner that the full supply voltage can be supplied to the storage capacitors within the memory cells without the need for driving the digit lines to the supply voltage.